The present invention relates to variable resistive memory devices, and more particularly to variable resistive memory devices having hierarchical wordline structures. As the demand for both high density and low power consumption continues to increase, a new generation of memory devices has emerged. The new generation of memory devices includes both nonvolatile characteristics for low power consumption and easy scalability for high density, There have been three basic types of the new generation memory devices, including Phase change Random Access Memory (PRAM), Resistive Random Access Memory (RRAM) and Magnetic Random Access Memory (MRAM).
As shown in FIG. 1, a unit memory cell for a memory device is indicated generally by the reference numeral 100. The unit memory cell 100 has a variable resistive material part 110 connected to a switching element 112, such as a transistor or a diode. Here, the variable resistive material part 110 and the switching element 112 are connected in series between a bitline BL and a wordline WL. In accordance with the particular characteristics of the variable resistive material part 110, the memory device may be one of PRAM, RRAM or MRAM. If the variable resistive material part 110 includes an upper electrode, a lower electrode, and phase change material between the upper and lower electrodes, the memory device may be classified as PRAM. If the variable resistive material part is made of upper and lower electrodes with a Complex Metal Oxide (COMO) between them, the memory device may be classified as RRAM. If the variable resistive material part is made of upper and lower electrodes, where the upper electrode is magnetic, with an insulating material between the electrodes, the memory device may be classified as MRAM.
A common characteristic of the three basic types of new generation memory devices is that a current flows from a bitline BL to a wordline WL, or vice versa, when a write operation or a read operation occurs. For simplicity of explanation, the description that follows assumes that the variable resistive material is a phase change material, but it shall be understood that the present disclosure extends to all types of new generation memory devices.
Turning to FIG. 2, a memory array or device 200 includes a plurality of unit memory cells 100 as described with respect to FIG. 1, The memory array 200 includes a row decoder and main wordline (MWL) driver 210 connected to memory blocks BLK0 through BLKn, main wordlines MWL_0 through MWL_I connected to each MWL driver respectively, sub wordline (SWL) drivers 220 each connected to one of the main wordlines MWL_0 through MWL_I, sub wordlines SWL each connected to sub wordline drivers of a main wordline, and bitlines BL in each memory block that connect through memory cells to the sub wordlines, Each sub wordline driver is located among the memory blocks and supplies appropriate voltage to the corresponding sub wordline in response to the main wordline voltage. The sub wordline drivers are of the inverter type, including a PMOS transistor 222 and an NMOS transistor 224. The PMOS 222 supplies high voltage to the sub wordline and the NMOS 224 supplies low voltage to the sub wordline.
Because each sub wordline driver has both PMOS and NMOS transistors, the layout for the sub wordline driver includes a well region to isolate each PMOS transistor from the corresponding NMOS transistor. Thus, the layout area for each sub wordline driver with well regions introduces a constraint on the minimum size for reducing the size of the memory array 200. In addition, because the voltage of a main wordline is different from that of sub wordline, if the main wordline and sub wordline became electrically shorted, such as due to a process problem, for example, repair may be difficult.